1. Field of the Invention
The present invention relates to a method of forming gate electrodes of semiconductor devices. More particularly, the present invention relates to a method of forming dual gate electrodes of a semiconductor device using polysilicon.
2. Description of the Related Art
In a recently developed complementary metal oxide semiconductor (CMOS) device, a buried channel is formed in a semiconductor substrate when a P-type MOS transistor is formed using polysilicon doped with N-type impurities. Additionally, a channel is formed near a surface of the semiconductor substrate when an N-type MOS transistor is formed using polysilicon doped with N-type impurities. When gate electrodes of the N-type and the P-type MOS transistors are formed using the polysilicon doped with the N-type impurities, the threshold voltage of the N-type MOS transistor may be different from that of the P-type MOS transistor. Such a difference in the threshold voltage between the N-type and P-type MOS transistors may serve as a limiting factor in the design and manufacture of the semiconductor device.
On the other hand, a semiconductor device that is to operate at a highly rapid response rate, such as a Fast SRAM or a logic device, comprises an N-type MOS transistor that includes a gate electrode composed of polysilicon doped with N-type impurities, and a P-type MOS transistor that includes a gate electrode composed of polysilicon doped with P-type impurities. This structure of the semiconductor device is generally referred to as a dual gate electrode structure.
FIGS. 1A and 1B illustrate a conventional method of forming dual gate electrodes of a semiconductor device.
Referring to FIG. 1A, an active region and a field region 10a are defined on a semiconductor substrate 10 using a general isolation process. A gate insulation film 12 is formed on the semiconductor substrate 10. An undoped polysilicon film is formed on the gate insulation film 12.
N-type impurities are selectively implanted into one portion of the undoped polysilicon film where an N-type metal oxide semiconductor (MOS) transistor will be formed. Then, P-type impurities are selectively implanted into another portion of the undoped polysilicon film where a P-type MOS transistor will be formed. Accordingly, a doped polysilicon film 14 is formed. However, the surface of the doped polysilicon film 14 is physically damaged as a result of the ion implantation processes.
Referring to FIG. 1B, the doped polysilicon film 14 is etched to form gate electrodes 16 of the N-type and P-type MOS transistors.
The above-described method for forming the dual gate electrodes is disclosed in Japanese Patent Laid-Open Publication No. 5-335503 as a way of minimizing a shifting of the threshold voltage of the P-type MOS transistor.
However, a pitting 18 of the active region of the semiconductor substrate 10 (hereinafter referred to as “active pitting 18”) may occur after the dual gate electrodes are formed. More specifically, the active pitting 18 occurs at portions of the active region adjacent to the gate electrode. The active pitting 18 occurs during the etching of the doped polysilicon film 14 to form the dual gate electrodes, and as the result of an over-etching of the doped polysilicon film 14.
The semiconductor device may fail or have poor characteristics when the transistors are disposed on portions of the substrate where the active pitting is present. As a result, the generation of active pitting lowers the manufacturing yield and reliability of semiconductor devices comprising a dual gate electrode structure.